1. Field of the Invention
The present invention generally relates to a memory system incorporated in a digital signal processor used in the field of mobile communications, such as time division multiple access (TDMA) systems, or the like, and more particularly to a memory system capable of simplifying the procedure of data storing processing.
2. Prior Art
The mobile communication system generally comprises a transmitter and a receiver, at least either of which is carried on a vehicle or a moving object for the communication through radio transmission. From such circumstances, the mobile communication system is generally subjected to the fading or similar phenomenon occurring in the moving circumstances, accompanied by state of radio transmission being fairly unstabilized. This is why the transmission error occurs so frequently in the mobile communications.
To solve this problem, it is effective to encode information data at the transmitter side so that, if any error is generated during radio transmission, such errors can be corrected later at the receiver side. Namely, the receiver side performs an error-correcting operation by decoding the transmitted information data. In such an error-correcting operation, the error-correcting accuracy will be improved by utilizing the information indicating the state of radio transmission through which the information data is propagated.
Meanwhile, when the mobile communication system employs the TDMA (time division multiple access) system, a predetermined time period is divided into a plurality of time slots respectively assigned or allocated to each of plural channels for multiplexing the information data.
In this case, there is the possibility that some trouble is concentrated on a specific part (specific time slot). To avoid fatal damage even in such serious conditions, a technology usually employed is an interleave operation according to which the order of time slots is intentionally varied in every cycle for allocating the information data. When the interleave operation is performed at the transmitter side, burst error can be preferably reduced or lightened to the level of random errors in favor of execution of error-correcting operation.
On the other hand, at the receiver side, a normally employed technology to decode such information data is a de-interleave operation according to which a reverse operation of the above-described interleave operation is performed to rearrange or reconstruct the data into the original form.
A digital signal processor, performing the decoding of digital signals, generally comprises a memory system for temporarily storing data generated during the computations. The de-interleave operation is normally performed in the process of storing the data into this memory system.
To this end, an address pointer designates an address in the memory system so as to intentionally switch the address in compliance with the principle of de-interleave in the process of storing data. By this operation, the decoded data are rearranged by the original order and stored in the memory system.
In this case, it is essential to assign a common address to one information data and its corresponding state-of-radio-transmission data so that they form combined or coupled data stored in a predetermined region of the memory system designated by the common address. The state-of-radio-transmission data represents the state of radio transmission through which each time slot carrying information data is propagated.
This kind of recording device, as shown in FIG. 1, comprises a memory element 11 memorizing information data and corresponding state-of-radio-transmission data, an address generating circuit 12 converting an address (ADR) on the program (hereinafter, referred to "program address (ADR)") into an inherent address of memory element 11, a judgement circuit 13 making a judgement based on the program address (ADR) as to whether or not memory element 11 is selected, an arithmetic circuit 14 generating data as a combination of information data and its corresponding state-of-radio-transmission data, and general purpose registers 15, 16 and 17 temporarily storing the result of arithmetic circuit 14.
The writing operation of this memory system is initiated upon entry of both the program address (ADR) and a write signal (WR). The program address (ADR), after being converted into the inherent address of memory element 11 by address generating circuit 12, is entered into memory element 11. The judgement circuit 13, when it identifies that the program address (ADR) is the address assigned to the memory element 11, generates a select signal indicating the fact that memory element 11 is selected.
In response to this select signal, the write signal (WR) is entered in memory element 11 after taking a logical product between the select signal and the write signal (WR). Then, any data entered from a data input/output terminal (I/O-c) is stored in a specific region of memory element 11 designated by the inherent address generated from address generating circuit 12.
Meanwhile, the reading operation of this memory system is initiated upon entry of both the program address (ADR) and a read signal (RD). The program address (ADR), after being converted into the inherent address of memory element 11 by address generating circuit 12, is entered into memory element 11. The judgement circuit 13, when it identifies that the program address (ADR) is the address assigned to the memory element 11, generates the select signal indicating the fact that memory element 11 is selected.
In response to this select signal, the read signal (RD) is entered in memory element 11 after taking a logical product between the select signal and the read signal (RD). Then, the data stored in the specific region of memory element 11 designated by the inherent address corresponding to the program address (ADR) are read out and outputted from the data input/output terminal (I/O-c).
The memory element 11 of this memory system, as illustrated in a memory map shown in FIG. 2, has a storage region designated by program address A(i,j) 18 for storing a combination of each information data .alpha.(i,j) 19 transmitted by time slot i and a corresponding state-of-radio-transmission data .beta.(i) 20. In the storage region covering address A(0,0) through A(0,n-1), the upper-digit region stores information data 19 transmitted by #0 time slot, while the lower-digit region stores state-of-radio-transmission data 20 inherent to #0 time slot.
Similarly, in the storage region covering address A(i,0) through A(i,n-1), the upper-digit region stores information data 19 transmitted by #i time slot, while the lower-digit region stores state-of-radio-transmission data 20 inherent to #i time slot.
The time slots, if their time slot numbers are identical, have common state-of-radio-transmission data 20 inherent to the same time slot. Hence, the storage region of #1 time slot, corresponding to address A(i,0) through A(i,n-1), has the same lower-digit data .beta.(i).
Each data, as a combination of one information data and its corresponding state-of-radio-transmission data, is produced by arithmetic circuit 14 using general purpose registers 15 through 17. FIG. 3 shows a flow chart illustrating the procedure for producing the combination of data, using #0 data and #1 data of #i time slot stored in address A(i,0) and address A(i,1).
Step 1: Arithmetic circuit 14 obtains a bit logical product (i.e. bit AND) between data 21 and data 22. The former data 21 has an upper-digit part representing unknown data and a lower-digit part representing state-of-radio-transmission data .beta.(i), while the latter data 22 has an upper-digit part representing 0 in each digit and a lower-digit part representing 1 in each digit. As a result of this bit AND calculation, arithmetic circuit 14 generates new data 23 having an upper-digit part representing storing 0 in each digit and a lower-digit part representing state-of-radio-transmission data .beta.(i). The newly created data 23 is stored in general purpose register B 16.
Step 2: Next, arithmetic circuit 14 obtains a bit logical product (i.e. bit AND) between data 24 and data 25. The former data 24 has an upper-digit part representing information data a(i,0) and a lower-digit part representing unknown data, while the latter data 25 has an upper-digit part representing 1 in each digit and a lower-digit part representing 0 in each digit. As a result of this bit AND calculation, arithmetic circuit 14 generates new data 26 having an upper-digit part representing information data a(i,0) and a lower-digit part representing 0 in each digit. The newly created data 26 is stored in general purpose register A 15.
Step 3: Subsequently, arithmetic circuit 14 obtains a bit logical product (i.e. bit OR) between data 26 stored in general purpose register A 15 and data 23 stored in general purpose register B 16, thus generating new data 27 as a result of this bit OR calculation. The newly created data 27 is stored in general purpose register C 17. At this moment, information data .alpha.(i,0) and state-of-radio-transmission data .beta.(i) inherent to #i time slot are coupled for the first time as one of combination data.
Step 4: Thus obtained data 27 is transferred into a storage region designated by address A(i,0) dedicated to #0 data of #i time slot.
Subsequently, #1 data of #i time slot to be stored in a storage region designated by address A(i,1) is created.
Step 5: Arithmetic circuit 14 obtains a bit logical product (i.e. bit AND) between data 28 and data 25. The former data 28 has an upper-digit part representing information data .alpha.(i,1) and a lower-digit part representing unknown data, while the latter data 25 has an upper-digit part representing 1 in each digit and a lower-digit part representing 0 in each digit. As a result of this bit AND calculation, arithmetic circuit 14 generates new data 29 having an upper-digit part representing information data .alpha.(i,1) and a lower-digit part representing 0 in each digit. The newly created data 29 is stored in general purpose register A 15.
For the same time slots, the state-of-radio-transmission data is common among them; therefore, the state-of-radio-transmission data for #i time slot can be specified as .beta.(i). Accordingly, data 23 used for creating #0 data of #i time slot and stored in general purpose register B 16 can be directly used as the state-of-radio-transmission data.
Step 6: Subsequently, arithmetic circuit 14 obtains a bit logical product (i.e. bit OR) between data 29 stored in general purpose register A 15 and data 23 stored in general purpose register B 16, thus generating new data 30 as a result of this bit OR calculation. The newly created data 30 is stored in general purpose register C 17. At this moment, information data .alpha.(i,1) and state-of-radio-transmission data .beta.(i) are coupled for the first time as one of combination data.
Step 7: Thus obtained data 30 is transferred into a storage region designated by address A(i,1) allocated to #1 data of #i time slot.
To accomplish the creation of all data of #i time slot, it is necessary to repeat the above-described operation until the data number reaches n-1. Accordingly, a total of 3n+1 steps will be required to accomplish the storage of all of #i time slot data into memory element 11.
However, according to the above-described conventional memory system, there is the problem that numerous preprocessing steps are required for the computations of bit AND, bit OR and others, before storing a combination of one information data and a corresponding state-of-radio-transmission data into the same storage region designated by a common address.